Synchronous electronic control system and system control method

ABSTRACT

The present invention is carried out to provide a system controller, a control system and a system control method which are inexpensive, highly stable, capable of storing all information and past record at a time when one of the devices is down and capable of switching the devices without any time lag. The system controller comprises a bus arbiter and a non-volatile memory and has only periodically executed functions and passive functions. The system includes a bus employing a center arbitration method, from which devices can be detached from and to which the detached devices can be attached again as power being supplied. Even if one of the devices is down, processes can be immediately continued by switching from the down device to other device by utilizing the system controller and the bus.

This application claims the benefit of PCT/JP2002/011243 filed Oct. 29,2004, which is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. FIELD OF INVENTION

The present invention relates to a system controller, a control systemand a system control method.

2. RELATED BACKGROUND ARTS

It has been a known technology to raise a reliability of a system inwhich a plurality of CPUs are arranged such that when one of the CPU isdown, the other CPU is started without interrupting operations of thesystem. Such technology is disclosed, for example, in Japanese laid openpatent No. 5-134932.

Hereinafter an outline of the disclosed technology is described asreferring to FIG. 5.

FIG. 5 is a block diagram illustrating the outline of the disclosedtechnology.

A reference numeral “1” is a first CPU board, “2” is a second CPU board,“10” is a common bus, “11” is a CPU, “12” is an arbiter to arbitratebetween an access requirement from the CPU 11 and an access requirementfrom a CPU 21, “13” and “14” are bus gates for determining flowingdirections of data under the control of the arbiter 12, “15” is an errordetection circuit for monitoring errors in one of the CPUs presentlyaccessing to a memory, “16” is a memory for storing processed data, “17”is an internal bus, “18” is a ready state monitoring circuit, “21” isthe CPU, “22” is an arbiter, “23” and “24” are bus gates, “25” is anerror detection circuit, “26” is a memory, “27” is an internal bus and“28” is a ready state monitoring circuit.

The first CPU board 1 comprises the CPU 11, the arbiter 12, the busgates 13 and 14, the error detection circuit 15 and the memory 16, andthe second CPU board 2 comprises the same components as those of thefirst CPU board 1.

The first CPU board 1 and the second CPU board 2 are arranged via thecommon bus 10 such that if an error is detected when the memory 16 ofthe first CPU board 1 is accessed, the arbiter 12 controls the bus gates13 and 14 so as to assign the access right to the second CPU board 2.

In addition to the above-described technology, other technology toutilize a reflect memory as a common memory, which can be accessed froma plurality of CPUs, and the like have been known.

However, in the above-mentioned technologies, since the access right isswitched in accordance with the detected error in one CPU by the errordetection circuit, there is a brief time lag from a time when the erroris caused to a time when the error is detected and the access right isswitched to the other CPU board. Sometimes problems are caused due tosuch time lag.

For example, if a CPU is down while processing data and writingprocessed data in a memory, the processed data by the CPU are lost andonly data written in the memory remain. Since an accident that the CPUis down is detected after the brief time lag, it is difficult to judgeto what extent the processed data are stored in the memory. Therefore,after the memory is returned a prior state before processing, the otherCPU must be started working for processing and writing data fromscratch. Alternatively, the other CPU must be started so as to succeedto processed data by the down CPU, after judging to what extent the dataremain in the memory as checking the data written in the memory.

Due to such time lag, it takes time to process data and a highlycomplicated function to switch the CPU from down one to the other isrequired. Further, in order to avoid such drawbacks a complicated systemor software with high performance is required, so that a considerableamount of costs are required or a stability of the system must besacrificed.

When a plurality of CPUs are employed, the reflect memory, which isexpensive, must be employed as the common memory for the CPUs so thatfurther costs are required.

The present invention is carried out in view of the above-mentionedproblems in order to provide an inexpensive, highly stable systemcontroller, a control system and a system control method capable ofstoring all information and past record when one of the CPUs is down andcapable of switching the access right without any time lag.

SUMMARY OF THE INVENTION

Hereinafter, technical substance of the present invention is disclosed.

-   -   (1) A control system comprising: a system controller comprising        a bus arbiter and a non-volatile memory and having only        periodically executed functions and passive functions; a bus        employing a center arbitration method, from which devices can be        detached and to which the detached devices can be attached again        as power being supplied; and a plurality of CPU boards which        execute the same processes synchronously, as devices arranged on        the bus, wherein: the system controller control the system to        continue processes only by periodically executed functions and        passive functions of a hardware structure of the system such        that when one of the CPU boards on the bus is down while        accessing to the non-volatile memory, the system controller        assigns the right to use the bus to other CPU board according to        a requirement from the other CPU board; and even if one of the        CPU board is down, the system is restored by detaching the down        CPU board from the bus and attaching the CPU board to the bus        again as power for the whole system being supplied.    -   (2) The system controller according to (1) further comprising a        duplex power source system having a plurality of power sources,        wherein: even if one of the CPU boards or power sources is down,        the system is restored by detaching the down CPU board or the        down power source from the bus and attaching the detached CPU        board or the detached power source to the bus again as power for        the whole system being supplied.    -   (3) The system controller according to (2) further comprising a        duplex IO board system having a plurality of IO boards, wherein:        the system controller control the system to continue processes        only by periodically executed functions and passive functions of        the hardware structure of the system such that when one of the        CPU boards or one of the IO boards on the bus is down while        accessing to the non-volatile memory, the system controller        assigns the right to use the bus to other CPU board or other IO        board of the duplex IO board system according to a requirement        from the other CPU board or the other IO board; and even if        either one of the CPU boards, the IO boards or the power sources        is down, the system is restored by detaching the down CPU board,        down IO board or down power source from the bus and attaching        the detached device to the bus again as power for the whole        system being supplied.    -   (4) A system control method for controlling a control system,        the control system comprising: a system controller comprising a        bus arbiter and a non-volatile memory and having only        periodically executed functions and passive functions; a bus        employing a center arbitration method from which devices can be        detached or to which the detached devices can be attached again        as power being supplied; and a plurality of CPU boards which        execute the same processes synchronously as devices arranged on        the bus, wherein: when one of the CPU boards on the bus is down        while accessing to the non-volatile memory, the system        controller assigns the right to use the bus to other CPU board        according to a requirement from the other CPU board so as to        continue processing; and the control system is restored by        detaching the down CPU board from the bus and attaching the        detached CPU board to the bus again as power for the whole        system being supplied.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a rough constitution of thecontrol system by the present invention.

FIG. 2 is a block diagram illustrating a constitution of the systemcontroller in an embodiment by the present invention.

FIG. 3 is a chart illustrating a non-stop control system by the presentinvention.

FIG. 4 is a flow chart illustrating a system control method by thepresent invention.

FIG. 5 is the block diagram illustrating the conventional art.

PREFERRED EMBODIMENT BY THE PRESENT INVENTION

Embodiments by the present invention are explained in detail asreferring to drawings.

Embodiments by the present invention are explained as referring to FIGS.1 to 4.

FIG. 1 is the block diagram illustrating the rough constitution of thecontrol system by the present invention.

In FIG. 1, a reference numeral “101” is a system controller having onlyperiodically executed functions and (passive) functions such as sendingclock signals, a bus arbiter, sending reset signals, sending IDSEL(Initialization Device Select) signals and the like, “102” is anon-volatile memory such as an SRAM or the like which can be accessedfrom devices on a common bus 201, “103” is a bus controller, “122” is abus arbiter which arbitrates access requirements from the devices(regardless of CPU boards or IO boards) and assigns the right to use thecommon bus to either one of the devices so that the assigned deviceaccesses to the non-volatile memory 102. The bus arbiter 122 may bemonolithically arranged with the bus controller 103.

A reference numeral “201” is a common bus such as a PCI (PeripheralComponent Interconnection) bus a compact PCI bus or the like, whichemploys a center arbitration method and from which devices can bedetached and to which devices can be attached again as power beingsupplied, “202” is bus gates, “301” is a first CPU board, “302” is aCPU, “311” is a second CPU board, “312” is a CPU, “401” is a first IOboard, “402” is a CPU, “411” is a second IO board and “412” is a CPU.

In the present embodiment the system controller 101 is arranged on thecommon bus 201. The system controller 101 comprises the non-volatilememory 102, the bus controller and the bus arbiter 122 used as commonresources.

Since the common bus 201 employs the center arbitration method anddevices can be detached from and attached to the common bus 201 again aspower being supplied, a system environment required for realizing acontinuous operation, i.e. a non-stop control can be arranged byfunctions of a hardware structure constituted by the system controller101 and the common bus 201.

Usually reasons why systems are down are attributed to software whileexecuting complicated operations, but such systems can be highlystabilized by a system environment for realizing non-stop operationsattained by the functions of the above-mentioned hardware structure.

On the common bus 201, the CPU boards 301, 311 and the IO boards 401,411 are constituted via the bus gates 202.

Respective CPUs 302, 312 on the CPU boards 301, 311 execute the sameprocesses synchronously, and either the CPU 302 or the CPU 312 isassigned the right to use the common bus 201 by the bus arbiter 122 sothat the assigned CPU accesses to the non-volatile memory 102 andreflects the processed results to the memory. The same processed resultsby the unassigned CPU are outputted, but not reflected.

In other words, the unassigned CPU executes the so-called dummyoperations, and repeatedly requests the bus arbiter 122 to assign theright to use the common bus 201, but is refused.

However, the moment either one of the CPUs 301, 302 is down, the busarbiter assigns the right to use the common bus 201 to the other CPUwhich can access to the non-volatile memory 102 in which information andpast record up to a time when the CPU is down, are stored. Thusprocesses are continued without interruption.

In this situation, since the non-volatile memory 201 can be accessed byeither one of the CPUs 302 or 312 in the same manner and since the CPUs301, 312 execute the same processes synchronously, the right to use thecommon bus can be switched without any time lag.

The CPU board equipped with the down CPU can restored by detaching theboard and attaching the detached CPU board to the common bus afterward.

Since power can be kept supplying while detaching and attaching the downboard, only small amounts of man-hours and costs for maintenance arerequired.

Hereinafter the system controller is explained in detail as referring toFIG. 2.

FIG. 2 is the block diagram illustrating the constitution of the systemcontroller in the embodiment by the present invention.

A reference numeral “111” is a module mounted on the system controller,“111 a” is a SIO (Special IO unit), “111 b” is a key switch 1, “111 c”is a key switch 2, “111 d” is PMC (PCI Mezzamine Card) connectors, “112”is a pin header with 26 pins, “113” is a dip switch, “114” is an LED,“115” is a rear connector, “116” is a bus buffer, “117” is a localcontroller, “118” is a reset circuit, “119” is a battery backup, “120”is a reset circuit, “121” is a configROM, “123” is an OCS (Oscillator),“124” is a clock DRV (Drive) and “125” is a DRV (Drive).

For example, in the present embodiment, an SRAM is employed as thenon-volatile memory 102, a PCI bus controller is employed as the buscontroller 103 and a compact PCI bus is employed as the common bus 201.

The system controller 101 is a system controller having onlyperiodically executed functions as a passive RAS (Remote Access Service)and passive functions, and comprising the non-volatile memory 102 suchas the SRAM or the like equipped with the battery backup 119. Thus, evenif either one of the CPU boards is down or detached from the common bus,data which should be commonly owned by the CPU boards can be maintainedby storing the data in the non-volatile memory 102.

By restricting functions of the system controller 101 to theperiodically executed functions and passive functions such as a functionto transmit clock signals, a function of the bus arbiter, a function totransmit reset signals, a function to transmit IDSEL signals and thelike, the system controller 101 is stabilized so that the whole controlsystem can be stabilized.

A plurality of devices such as the CPU boards, the IO boards and thelike may be arranged in the common bus 201 via the bus gates 202.

Hereinafter, the non-stop control system by the present invention isexplained as referring to FIG. 3.

FIG. 3 is the chart illustrating the non-stop control system by thepresent invention.

Reference numerals “501”, “502”, “503” and “504” are IO boards and“601”, “602” are power sources such as hot-swap power sources or thelike. The power sources 601 and 602 constitute a duplex power sourcesystem.

Universal CPU boards for personal computers can be employed as the CPUboards 301, 311. By employing, for example, a PCI bridge chip 21554called an embedded bridge as a PCI bridge, the non-stop control systemcan support an operation for detaching devices from and attaching thedetached devices to the common bus again (hereinafter also referred as“Hot-Swap”) as a standard operation as power being supplied.

LAN and IDE (Integrated Drive Electronics) may be employed for inputtingdata to and outputting data from the CPU boards 301, 311 by utilizing aROM in which an operating system is stored. A hard disk drive may beemployed instead.

The CPU boards 301, 311 have piggy pack connectors (not shown) to whichLAN cards can be added when a duplex LAN system is required.

It is not necessary to employ the CPU boards 301, 311 of highperformance for the non-stop control system, but the CPU boards may beconverted into an ultra high speed parallel processing system byemploying a board equipped with a dual processor or the like which runsthe CPU boards in parallel.

In stead of accessing to the IO boards 501 to 504 directly from the CPUboards 301, 302, a carry of an IP module may be arranged so as totransfer data accessed by a processor exclusively used for controllingthe IO boards to a memory designated beforehand as the whole systembeing synchronized.

The duplex power sources 601, 602 are already put to practical use. TheCPU boards 301, 311 may have respective HDDs or the like as far as datastored in the HDDs are common.

As the control system is arranged in the above-mentioned way, a non-stopcontrol system which runs the system controller 101 and a plurality ofdevices comprising the CPU boards 301, 311, the IO boards 501 to 504 andthe duplex power system comprising power sources 601, 602, can berealized. And the Hot-Swap makes it possible to reduce costs formaintaining the system to a larger extent.

Further, power sources, CPUs and IO controllers for general-purpose use,namely, open systems can be used by employing a general-purpose bus suchas the compact PCI bus or the like. Since these general-purpose devicescan be Hot-Swapped, being daily improved devices such as the CPU boardsand the like with high quality can be employed as required so that acontrol system with a high flexibility and the easy maintenance of thesystem can be realized.

Hereinafter, the system control method is explained as referring to FIG.4.

FIG. 4 is the flow chart illustrating the system control method by thepresent invention.

When the control system is started, the respective CPUs 302 and 312execute the same processes synchronously at step S1001.

At step S1002, the bus arbiter 122 assigns the right to use the commonbus 201 to either one of the CPU boards 301, 311 and processed resultsby the assigned CPU board are reflected to the non-volatile memory.

At step S1003, either one of the CPU board 301 or 312 is down due to acaused error in the CPU board.

At step S1004, whether the down CPU board has accessed to thenon-volatile memory 102 or not is judged.

If the down CPU board has not accessed to the memory, the control systemruns without interruption (step S1006).

If the down CPU board has accessed to the memory, and since the down CPUboard has not use the common bus 201 anymore, the bus arbiter 122immediately assigns the right to use the common bus 201 to the other CPUboard (step 1005) so that the processed results by the assigned CPUboard are reflected to the non-volatile memory 102 without any time lag.

Thus the control system continues its processes (step S1006).

Later at step S1007, the down CPU board including the down CPU isdetached from the system and the detached CPU board is attached to thesystem again (Hot-Swap), so that the system is restored.

In the above-mentioned way, not only a highly stable non-stop controlcapable of being continuously operated limitlessly can be realized, butalso costs for maintaining the system can be remarkably reduced.

The present method is explained with respect to the CPU boards, but itcan be applied to the IO boards and other devices in the same way.

POSSIBILITIES OF INDUSTRIAL USE

Consequently, the present invention can provide the system controller,the control system and the system control method which are inexpensive,highly stable, capable of storing all information and past record andcapable of switching the devices without any time lag.

By employing the center arbitration method and the bus capable ofswapping the down devices as power being supplied, a system controlmethod capable of storing all information and past record at a time whenthe device is down, capable of switching the devices without any timelag and capable of reducing the maintenance costs remarkably can berealized.

Further a stable control system with high performance can be realized byutilizing the open system.

1. A control system comprising: a system controller comprising a busarbiter and a non-volatile memory and having only periodically executedfunctions and passive functions; a bus employing a center arbitrationmethod, wherein a single bus arbiter is connected to a plurality of CPUsvia the bus, from which devices can be detached and to which thedetached devices can be attached again as power being supplied; and aplurality of CPU boards which execute the same processes synchronously,as devices arranged on said bus, wherein: said system controller controlthe system to continue processes only by periodically executed functionsand passive functions of a hardware structure of the system such thatwhen one of said CPU boards on said bus is down while accessing to saidnon-volatile memory, said system controller assigns the right to usesaid bus to other CPU board according to a requirement from said otherCPU board; and even if one of the CPU boards is down, the system isrestored by detaching said down CPU board from said bus and attachingsaid detached CPU board to said bus again as power for the whole systembeing supplied.
 2. The control system according to claim 1 furthercomprising a duplex power source system having a plurality of powersources, wherein: even if one of the CPU boards or power sources isdown, the system is restored by detaching said down CPU board or saiddown power source from said bus and attaching said detached CPU board orsaid detached power source to said bus again as power for the wholesystem being supplied.
 3. A control system comprising: a systemcontroller comprising a bus arbiter and a non-volatile memory and havingonly periodically executed functions and passive functions; a busemploying a center arbitration method, wherein a single bus arbiter isconnected to a plurality of CPUs via the bus, from which devices can bedetached and to which the detached devices can be attached again aspower being supplied; and a plurality of CPU boards which execute thesame processes synchronously, as devices arranged on said bus, wherein:said system controller control the system to continue processes only byperiodically executed functions and passive functions of a hardwarestructure of the system such that when one of said CPU boards on saidbus is down while accessing to said non-volatile memory, said systemcontroller assigns the right to use said bus to other CPU boardaccording to a requirement from said other CPU board; and even if one ofthe CPU boards is down, the system is restored by detaching said downCPU board from said bus and attaching said detached CPU board to saidbus again as power for the whole system being supplied, furthercomprising a duplex power source system having a plurality of powersources, wherein even if one of the CPU boards or power sources is down,the system is restored by detaching said down CPU board or said downpower source from said bus and attaching said detached CPU board or saiddetached power source to said bus again as power for the whole systembeing supplied, further comprising a duplex IO board system having aplurality of IO boards, wherein: said system controller control thesystem to continue processes only by periodically executed functions andpassive functions of the hardware structure of the system such that whenone of said CPU boards or one of said IO boards on said bus is downwhile accessing to said non-volatile memory, said system controllerassigns the right to use said bus to other CPU board or other IO boardof said duplex IO board system according to a requirement from saidother CPU board or said other IO board; and even if either one of theCPU boards, the IO boards or the power sources is down, the system isrestored by detaching said down CPU board, down IO board or down powersource from said bus and attaching said detached device to said busagain as power for the whole system being supplied.
 4. A system controlmethod for controlling a control system, said control system comprising:a system controller comprising a bus arbiter and a non-volatile memoryand having only periodically executed functions and passive functions; abus employing a center arbitration method from which devices can bedetached and to which the detached devices can be attached again aspower being supplied; and a plurality of CPU boards which execute thesame processes synchronously as devices arranged on said bus, wherein:when one of said CPU boards on said bus is down while accessing to saidnon-volatile memory, said system controller assigns the right to usesaid bus to other CPU board according to a requirement from said otherCPU board so as to continue processing; and said control system isrestored by detaching said down CPU board from said bus and attachingsaid detached CPU board to said bus again as power for the whole systembeing supplied.